The Neurotech Industry Workgroup aims at bringing together actors in neuromorphic computing interested in applications and industrial concerns. Our online seminar series will highlight companies interested in building neuromorphic hardware, creating tools for neuromorphic or using neuromorphic hardware.

Upcoming Events


The first part of the event (approx. 1h) consists in short talks from industrial actors. The second part (approx. 30 min) will be a panel session, aimed at answering questions from the audience and debating.


No further events are planned at the moment.

Latest Event

Industry Workgroup Webinar: "How can one make money with Neuromorphic Technologies?"

22 February, 2021

Dr. Dylan Muir, PhD


Director, Algorithm and Applications
Director, Global Business Development

Dylan Muir is a specialist in architectures for neuromorphic computation. He has published extensively in computational and experimental neuroscience. At SynSense he is responsible for directing development of neural architectures for signal processing, as well as business development. Dr. Muir holds a Doctor of Science (PhD) from ETH Zürich, and undergraduate degrees (Masters) in Electronic Engineering and in Computer Science from QUT, Australia.

Pierre Bessière


Conseiller scientifique/Business Angel

Pierre Bessière (born in 1958) received the engineering degree (1981) and the PhD degree (1983) in computer science from the Institut National Polytechnique de Grenoble (INPG). He did a Post-Doctorate at SRI International (Stanford Research Institute) working on a project for NASA. He then worked for five years in an industrial company as the leader of different artificial intelligence projects. He came back to research in 1989. He has been a senior researcher at CNRS since 1992. His main research concerns have been evolutionary algorithms and probabilistic reasoning. He leads the Bayesian Programming research group on these two subjects. He is a co-founder and scientific adviser of the ProbaYes Company, created in 2003, which develops and sells Bayesian solutions for the industry. ProbaYes joined the La Poste group in 2016. He is a co-founder and scientific adviser of created in 2019.

Menno Lindwer

GrAI Matter Labs

VP IP&Silicon, GrAI Matter Labs
Managing Director, GrAI Matter Labs

Menno Lindwer is leading GML’s hardware development department, which includes developing neuromorphic and neural network processors. Prior to joining GML, Menno was Processor Technology Architect, Engineering Manager, and Program Manager at Intel.

He received his from Twente University and his PDEng from Eindhoven University in 1993. Since then, he studied asynchronous devices, database matching technology, 3D graphics renderers, media processor design, and AI processors. In 1995, he joined Philips Research, working on the design of Java and Media processors. In 2002, he was part of the team that started up Silicon Hive. He was director of product management for Silicon Hive’s HiveLogic parallel processing platform. Silicon Hive was acquired by Intel in February 2011. At Intel, Menno led teams that worked on processor construction tools and optimizing auto-targeting compilers. Also, Menno led Intel's activities in several EU projects.

Menno’s work has led to over 30 scientific articles and patent publications (seven patents currently assigned in the US). His interests include low-power computing systems, neuromorphic and neural network processors, and spatial compilers. Menno served on the executive committee and technical program committees of the DATE conference. He co-authored several articles on Ambient Intelligence at DATE, on media processing at IEEE ISM, GSPX, on compiler technology in IJPP, and on design space exploration for multi-ASIP systems.

Laurent Daudet


CTO & Co-Founder

Laurent Daudet is currently on leave from his position of full Professor of Physics at the Université Paris Diderot, Paris. He is a graduate from Ecole Normale Supérieure and holds a PhD in Applied Mathematics from Marseille University. He is a former fellow of the Institut Universitaire de France, which recognizes the top 2% of French university professors for their research excellence. In parallel, he held various academic positions : Visiting Scholar at Stanford University, USA, Visiting Senior Lecturer at Queen Mary University of London, UK, Visiting Professor at the National Institute for Informatics in Tokyo, Japan. Laurent has been a consultant to various small and large companies, and is a co-inventor in several patents. Laurent is also a Senior Member of the IEEE and an elected member of the IEEE AASP Technical Committee as well as a former Associate Editor of IEEE TSALP. He has co-authored more than 50 peer-reviewed journal articles, and over 120 conference proceedings.